1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that includes a level shift circuit.
2. Description of Related Art
Semiconductor devices such as a dynamic random access memory (DRAM) include various types of peripheral circuits that operate on an internal power supply voltage lower than an external power supply voltage in order to reduce power consumption. In such a case, there is a difference in amplitude between an internal data signal and an external data signal. A level shift circuit therefore needs to be inserted into the signal path so that the amplitude of the internal data signal is converted into that of the external data signal before the data is output to outside.
Converting a level of an internal data signal by using a level shift circuit may change the duty ratio of the internal data signal. The reason is that there is a difference between the rising time and falling time of the level shift circuit. To solve the problem, Japanese Patent Application Laid-Open Nos. 2004-40262 and 2004-153689 propose methods of connecting a pair of level shift circuits, which are opposite each other in conductivity types, in parallel.
In the level shift circuits described in Japanese Patent Application Laid-Open Nos. 2004-40262 and 2004-153689, in-phase output signals output from the pair of level shift circuits are short-circuited. Therefore, a through current can flow depending on a difference in operating speed between the pair of the level shift circuits. A level shift circuit has thus been desired that resolves the difference between the rising time and falling time and prevents the occurrence of a through current.